# Design Documentation for sg13g2_or4_2

## Substrate
```
  0123456789012345
4 SSSSSSSSSSSSSSSS
3 NNNNNNNNNNNNNNNN
2 NNNNNNNNNNNNNNNN
1 NNNNNNNNNNNNNNNN
0 NNNNNNNNNNNNNNNN
9 NNNNNNNNNNNNNNNN
8 NNNNNNNNNNNNNNNN
7 NNNNNNNNNNNNNNNN
6 SSSSSSSSSSSSSSSS
5 SSSSSSSSSSSSSSSS
4 SSSSSSSSSSSSSSSS
3 SSSSSSSSSSSSSSSS
2 SSSSSSSSSSSSSSSS
1 SSSSSSSSSSSSSSSS
0 NNNNNNNNNNNNNNNN
```
Legend: N=N-Well, S=Substrate

## Active
```
  0123456789012345
4 pppppppppppppppp
3
2
1  pppppppppppppp
0  pppppppppppppp
9  pppppppppppppp
8           ppppp
7
6
5
4  nnnnnnnnnnnnnn
3  nnnnnnnnnnnnnn
2
1
0 nnnnnnnnnnnnnnnn
```
Legend: n=NMOS Active, p=PMOS Active

## Polysilicon
```
  0123456789012345
4
3
2     G  G G   G
1     G  G G   G
0     G  G G   G
9     G  G G   G
8     G  G G   G
7   G G GGGG   G
6     G  GGGGGG
5     G  G G   G
4     G  G G   G
3     G  G G   G
2              G
1
0
```
Legend: G=Polysilicon

## Metal 1
```
  0123456789012345
4 &+&+&+&+&+&+&+&+
3           +   +
2  c        & c &
1  C        + O +
0  c        & o &
9  C          O +
8  c        C o c
7  II IIIIIIC O
6  IIcIiIiiIcCO
5    CCCCCCCC O
4  c c c  c c o _
3  - C -  C - O -
2  -   -    - c _
1  -   -    -   -
0 _-_-_-_-_-_-_-_-
```
Legend: +/&=VDD, -/_=VSS, I/i=Metal 1 Input, O/o=Metal 1 Output, c/i/o/&/_=Contacted metal (lowercase)

## Connectivity Matrix

| Silicon | VDD | VSS | Input1 | Internal1 | Internal2 | Output1 |
| --- | --- | --- | --- | --- | --- | --- |
| NMOS1 |   | X |   |   |   |   |
| NMOS2 |   | X |   | X |   | X |
| PMOS1 | X |   |   |   | X | X |
| PMOS2 | X |   |   |   |   |   |
| Poly1 |   |   |   |   |   |   |
| Poly2 |   |   |   |   |   |   |
| Poly3 |   |   | X | X |   |   |
| Poly4 |   |   |   |   |   |   |
| Poly5 |   |   |   |   |   |   |

## Silicon Neighbourhood

| Silicon | Poly1 | Poly2 | Poly3 | Poly4 | Poly5 |
| --- | --- | --- | --- | --- | --- |
| NMOS1 |   |   |   |   |   |
| NMOS2 | O | O | O |   |   |
| PMOS1 |   | O | O |   | O |
| PMOS2 |   |   |   |   |   |