# Design Documentation for sg13g2_or3_2

## Substrate
```
  01234567890123
4 SSSSSSSSSSSSSS
3 NNNNNNNNNNNNNN
2 NNNNNNNNNNNNNN
1 NNNNNNNNNNNNNN
0 NNNNNNNNNNNNNN
9 NNNNNNNNNNNNNN
8 NNNNNNNNNNNNNN
7 NNNNNNNNNNNNNN
6 SSSSSSSSSSSSSS
5 SSSSSSSSSSSSSS
4 SSSSSSSSSSSSSS
3 SSSSSSSSSSSSSS
2 SSSSSSSSSSSSSS
1 SSSSSSSSSSSSSS
0 NNNNNNNNNNNNNN
```
Legend: N=N-Well, S=Substrate

## Active
```
  01234567890123
4 pppppppppppppp
3
2
1  pppppppppppp
0  pppppppppppp
9  pppppppppppp
8  pppppppppppp
7
6
5
4  nnnnnnnnnnnn
3  nnnnnnnnnnnn
2
1
0 nnnnnnnnnnnnnn
```
Legend: n=NMOS Active, p=PMOS Active

## Polysilicon
```
  01234567890123
4
3
2       G  G G
1       G  G G
0       G  G G
9       G  G G
8       G  G G
7   G G GG GGG
6   G G GG GGG
5            G
4            G
3            G
2            G
1
0
```
Legend: G=Polysilicon

## Metal 1
```
  01234567890123
4 &+&+&+&+&+&+&+
3        ++   +
2        ++ c &
1  C     ++ O +
0  c     && o &
9  C        O +
8  cCCCCCCC c c
7  II IIII
6  iI IiIicC OO
5
4  C   CC   o _
3  C - CC - O -
2  c _ c c_ c _
1    -    -   -
0 _-_-_-_-_-_-_-
```
Legend: +/&=VDD, -/_=VSS, I/i=Metal 1 Input, O/o=Metal 1 Output, c/i/o/&/_=Contacted metal (lowercase)

## Connectivity Matrix

| Silicon | VDD | VSS | Input2 | Internal4 | Output1 | Output3 |
| --- | --- | --- | --- | --- | --- | --- |
| NMOS1 |   | X |   |   |   |   |
| NMOS2 |   | X |   |   | X |   |
| PMOS1 | X |   |   | X |   | X |
| PMOS2 | X |   |   |   |   |   |
| Poly1 |   |   |   |   |   |   |
| Poly2 |   |   |   |   |   |   |
| Poly3 |   |   |   |   |   |   |
| Poly4 |   |   | X |   |   |   |

## Silicon Neighbourhood

| Silicon | Poly1 | Poly2 | Poly3 | Poly4 |
| --- | --- | --- | --- | --- |
| NMOS1 |   |   |   |   |
| NMOS2 | O |   |   |   |
| PMOS1 | O | S | S | O |
| PMOS2 |   |   |   |   |