# Design Documentation for sg13g2_or3_1

## Substrate
```
  012345678901
4 SSSSSSSSSSSS
3 NNNNNNNNNNNN
2 NNNNNNNNNNNN
1 NNNNNNNNNNNN
0 NNNNNNNNNNNN
9 NNNNNNNNNNNN
8 NNNNNNNNNNNN
7 NNNNNNNNNNNN
6 SSSSSSSSSSSS
5 SSSSSSSSSSSS
4 SSSSSSSSSSSS
3 SSSSSSSSSSSS
2 SSSSSSSSSSSS
1 SSSSSSSSSSSS
0 NNNNNNNNNNNN
```
Legend: N=N-Well, S=Substrate

## Active
```
  012345678901
4 pppppppppppp
3
2
1  pppppppppp
0  pppppppppp
9  pppppppppp
8  pppppppppp
7
6
5
4  nnnnnnnnnn
3  nnnnnnnnnn
2
1
0 nnnnnnnnnnnn
```
Legend: n=NMOS Active, p=PMOS Active

## Polysilicon
```
  012345678901
4
3
2       G  G
1       G  G
0       G  G
9       G  G
8       G  G
7   G G GG G
6   G G GG G
5
4
3
2
1
0
```
Legend: G=Polysilicon

## Metal 1
```
  012345678901
4 &+&+&+&+&+&+
3        ++
2        ++ c
1  C     ++ O
0  c     && o
9  C        O
8  cCCCCCCC c
7  II IIII
6  iI IiIicC
5
4  C   CC   o
3  C - CC - O
2  c _ c c_ c
1    -    -
0 _-_-_-_-_-_-
```
Legend: +/&=VDD, -/_=VSS, I/i=Metal 1 Input, O/o=Metal 1 Output, c/i/o/&/_=Contacted metal (lowercase)

## Connectivity Matrix

| Silicon | VDD | VSS | Input2 | Internal4 | Output1 | Output2 |
| --- | --- | --- | --- | --- | --- | --- |
| NMOS1 |   | X |   |   |   |   |
| NMOS2 |   |   |   |   | X |   |
| PMOS1 | X |   |   | X |   | X |
| PMOS2 | X |   |   |   |   |   |
| Poly1 |   |   |   |   |   |   |
| Poly2 |   |   |   |   |   |   |
| Poly3 |   |   | X |   |   |   |
| Poly4 |   |   |   |   |   |   |

## Silicon Neighbourhood

| Silicon | Poly1 | Poly2 | Poly3 | Poly4 |
| --- | --- | --- | --- | --- |
| NMOS1 |   |   |   |   |
| NMOS2 |   |   |   |   |
| PMOS1 | S | S | O | O |
| PMOS2 |   |   |   |   |