# Design Documentation for sg13g2_or2_2

## Substrate
```
  01234567890
4 SSSSSSSSSSS
3 NNNNNNNNNNN
2 NNNNNNNNNNN
1 NNNNNNNNNNN
0 NNNNNNNNNNN
9 NNNNNNNNNNN
8 NNNNNNNNNNN
7 NNNNNNNNNNN
6 SSSSSSSSSSS
5 SSSSSSSSSSS
4 SSSSSSSSSSS
3 SSSSSSSSSSS
2 SSSSSSSSSSS
1 SSSSSSSSSSS
0 NNNNNNNNNNN
```
Legend: N=N-Well, S=Substrate

## Active
```
  01234567890
4 ppppppppppp
3
2  ppppppppp
1  ppppppppp
0  ppppppppp
9      ppppp
8
7
6
5
4      nnnnn
3  nnnnnnnnn
2  nnnnnnnnn
1
0 nnnnnnnnnnn
```
Legend: n=NMOS Active, p=PMOS Active

## Polysilicon
```
  01234567890
4
3         G
2         G
1         G
0         G
9         G
8   G     G
7    GG   G
6    GG   G
5      GGGG
4         G
3         G
2         G
1         G
0
```
Legend: G=Polysilicon

## Metal 1
```
  01234567890
4 &+&+&+&+&+&
3      +   +
2  c   & oc+
1  C   + O +
0  c I & oc+
9  C I + O +
8  CIi   O
7  C II  O
6  C i c O
5  C I C O
4  CCCCC oc-
3    C   O -
2  _ c _ oc-
1  -   -   -
0 _-_-_-_-_-_
```
Legend: +/&=VDD, -/_=VSS, I/i=Metal 1 Input, O/o=Metal 1 Output, c/i/o/&/_=Contacted metal (lowercase)

## Connectivity Matrix

| Silicon | VDD | VSS | Input1 | Internal1 | Output1 |
| --- | --- | --- | --- | --- | --- |
| NMOS1 |   | X |   |   |   |
| NMOS2 |   | X |   | X | X |
| PMOS1 | X |   |   | X | X |
| PMOS2 | X |   |   |   |   |
| Poly1 | X | X |   |   |   |
| Poly2 |   |   | X |   |   |
| Poly3 |   |   |   |   |   |

## Silicon Neighbourhood

| Silicon | Poly1 | Poly2 | Poly3 |
| --- | --- | --- | --- |
| NMOS1 | N |   |   |
| NMOS2 | O |   |   |
| PMOS1 | O |   |   |
| PMOS2 | S |   |   |