# Design Documentation for sg13g2_nor2_1

## Substrate
```
  0123456
4 SSSSSSS
3 NNNNNNN
2 NNNNNNN
1 NNNNNNN
0 NNNNNNN
9 NNNNNNN
8 NNNNNNN
7 NNNNNNN
6 SSSSSSS
5 SSSSSSS
4 SSSSSSS
3 SSSSSSS
2 SSSSSSS
1 SSSSSSS
0 NNNNNNN
```
Legend: N=N-Well, S=Substrate

## Active
```
  0123456
4 ppppppp
3
2
1  ppppp
0  ppppp
9  ppppp
8  ppppp
7
6
5
4  nnnnn
3  nnnnn
2
1
0 nnnnnnn
```
Legend: n=NMOS Active, p=PMOS Active

## Polysilicon
```
  0123456
4
3
2
1
0
9
8
7
6  GG GG
5
4
3
2
1
0
```
Legend: G=Polysilicon

## Metal 1
```
  0123456
4 &+&+&+&
3  +
2  &   c
1  +   O
0  &   o
9  + OOO
8  c O c
7    O
6  iIO i
5    O
4  _ o _
3  - O -
2  _ c _
1  -   -
0 _-_-_-_
```
Legend: +/&=VDD, -/_=VSS, I/i=Metal 1 Input, O/o=Metal 1 Output, c/i/o/&/_=Contacted metal (lowercase)

## Connectivity Matrix

| Silicon | VDD | VSS | Input1 | Input2 | Output1 |
| --- | --- | --- | --- | --- | --- |
| NMOS1 |   | X |   |   |   |
| NMOS2 |   | X |   |   | X |
| PMOS1 | X |   |   |   | X |
| PMOS2 | X |   |   |   |   |
| Poly1 |   |   | X |   |   |
| Poly2 |   |   |   | X |   |