# Design Documentation for sg13g2_a22oi_1

## Substrate
```
  01234567890
4 SSSSSSSSSSS
3 NNNNNNNNNNN
2 NNNNNNNNNNN
1 NNNNNNNNNNN
0 NNNNNNNNNNN
9 NNNNNNNNNNN
8 NNNNNNNNNNN
7 NNNNNNNNNNN
6 SSSSSSSSSSS
5 SSSSSSSSSSS
4 SSSSSSSSSSS
3 SSSSSSSSSSS
2 SSSSSSSSSSS
1 SSSSSSSSSSS
0 NNNNNNNNNNN
```
Legend: N=N-Well, S=Substrate

## Active
```
  01234567890
4 ppppppppppp
3
2  ppppppppp
1  ppppppppp
0  ppppppppp
9  ppppppppp
8
7
6
5
4  nnnnnnnnn
3  nnnnnnnnn
2  nnnnnnnnn
1
0 nnnnnnnnnnn
```
Legend: n=NMOS Active, p=PMOS Active

## Polysilicon
```
  01234567890
4
3
2     G G G
1     G G G
0     G G G
9     G G G
8     G G G
7  G  GGGGGG
6   GGGG  G
5     GG GG
4         G
3         G
2         G
1
0
```
Legend: G=Polysilicon

## Metal 1
```
  01234567890
4 &+&+&+&+&+&
3  +       +
2  & cCCCc +c
1  + C   C +
0  & c o c +c
9  +   O I +
8  c i o i  c
7  I IIO III
6  I   O cII
5   I  O III
4  _I  o I -c
3  -I    I -
2  _IIIIII -c
1  -       -
0 _-_-_-_-_-_
```
Legend: +/&=VDD, -/_=VSS, I/i=Metal 1 Input, O/o=Metal 1 Output, c/i/o/&/_=Contacted metal (lowercase)

## Connectivity Matrix

| Silicon | VDD | VSS | Internal1 | Output1 |
| --- | --- | --- | --- | --- |
| NMOS1 |   | X |   |   |
| NMOS2 |   | X |   | X |
| PMOS1 | X |   | X | X |
| PMOS2 | X |   |   |   |
| Poly1 |   |   |   |   |
| Poly2 |   |   |   |   |

## Silicon Neighbourhood

| Silicon | Poly1 | Poly2 |
| --- | --- | --- |
| NMOS1 |   |   |
| NMOS2 | O |   |
| PMOS1 | O |   |
| PMOS2 |   |   |