# Design Documentation for sg13g2_a21oi_2

## Substrate
```
  01234567890123
4 SSSSSSSSSSSSSS
3 NNNNNNNNNNNNNN
2 NNNNNNNNNNNNNN
1 NNNNNNNNNNNNNN
0 NNNNNNNNNNNNNN
9 NNNNNNNNNNNNNN
8 NNNNNNNNNNNNNN
7 NNNNNNNNNNNNNN
6 SSSSSSSSSSSSSS
5 SSSSSSSSSSSSSS
4 SSSSSSSSSSSSSS
3 SSSSSSSSSSSSSS
2 SSSSSSSSSSSSSS
1 SSSSSSSSSSSSSS
0 NNNNNNNNNNNNNN
```
Legend: N=N-Well, S=Substrate

## Active
```
  01234567890123
4 pppppppppppppp
3
2
1  pppppppppppp
0  pppppppppppp
9  pppppppppppp
8  pppppppppppp
7
6
5  nnnnnnnnnnnn
4  nnnnnnnnnnnn
3  nnnnnnnnnnnn
2
1
0 nnnnnnnnnnnnnn
```
Legend: n=NMOS Active, p=PMOS Active

## Polysilicon
```
  01234567890123
4
3
2   G G
1   G G
0   G G
9   G G
8   G G
7   G GG GG GGG
6   G GG GG GGG
5   G G
4   G G
3   G G
2   G G
1
0
```
Legend: G=Polysilicon

## Metal 1
```
  01234567890123
4 &+&+&+&+&+&+&+
3    +   +
2  c & c &c   c
1  C + C + CCCC
0  cCCCcCCc o c
9           O
8  IIIIIIII o I
7  II II  I O I
6  iI Ii  i O i
5           O
4  _ c o cc o _
3  - C O C  O -
2  - CCCCC    -
1  -          -
0 _-_-_-_-_-_-_-
```
Legend: +/&=VDD, -/_=VSS, I/i=Metal 1 Input, O/o=Metal 1 Output, c/i/o/&/_=Contacted metal (lowercase)

## Connectivity Matrix

| Silicon | VDD | VSS | VSS2 | Input1 | Input2 | Internal1 | Internal2 | Internal3 | Output1 | Output2 |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| NMOS1 |   | X |   |   |   |   |   |   |   |   |
| NMOS2 |   | X | X |   |   | X |   |   | X | X |
| PMOS1 |   |   |   |   |   |   | X | X |   | X |
| PMOS2 | X |   |   |   |   |   |   |   |   |   |
| Poly1 |   |   |   |   |   |   |   |   |   |   |
| Poly2 |   |   |   | X |   |   |   |   |   |   |
| Poly3 |   |   |   | X |   |   |   |   |   |   |
| Poly4 |   |   |   |   | X |   |   |   |   |   |

## Silicon Neighbourhood

| Silicon | Poly1 | Poly2 | Poly3 | Poly4 |
| --- | --- | --- | --- | --- |
| NMOS1 |   |   |   |   |
| NMOS2 | O | O | N | N |
| PMOS1 | O | O | S | S |
| PMOS2 |   |   |   |   |