# Design Documentation for sg13g2_a21o_2

## Substrate
```
  01234567890123
4 SSSSSSSSSSSSSS
3 NNNNNNNNNNNNNN
2 NNNNNNNNNNNNNN
1 NNNNNNNNNNNNNN
0 NNNNNNNNNNNNNN
9 NNNNNNNNNNNNNN
8 NNNNNNNNNNNNNN
7 NNNNNNNNNNNNNN
6 SSSSSSSSSSSSSS
5 SSSSSSSSSSSSSS
4 SSSSSSSSSSSSSS
3 SSSSSSSSSSSSSS
2 SSSSSSSSSSSSSS
1 SSSSSSSSSSSSSS
0 NNNNNNNNNNNNNN
```
Legend: N=N-Well, S=Substrate

## Active
```
  01234567890123
4 pppppppppppppp
3
2  ppppp
1  ppppp ppppppp
0  ppppp ppppppp
9  ppppp ppppppp
8  ppppp
7
6
5  nnnnn nnnnnnn
4  nnnnn nnnnnnn
3  nnnnn nnnnnnn
2
1
0 nnnnnnnnnnnnnn
```
Legend: n=NMOS Active, p=PMOS Active

## Polysilicon
```
  01234567890123
4
3
2   G G
1   G G
0   G G
9   G G
8   G G
7   GGGG  G G G
6   G G     G
5   G G     G
4   G G     G
3   G G     G
2   G G     G
1
0
```
Legend: G=Polysilicon

## Metal 1
```
  01234567890123
4 &+&+&+&+&+&+&+
3  +   +     C
2  & c & cc cCc
1  + O + C C C C
0  & o & ccCcCcC
9  + O + C C   C
8  c o c cc   c
7    O CCCI I I
6    O c Ci i i
5    O   CCC
4  _ o _ c Cc c-
3  - O - - C   -
2  -   - -     -
1  -   - -     -
0 _-_-_-_-_-_-_-
```
Legend: +/&=VDD, -/_=VSS, I/i=Metal 1 Input, O/o=Metal 1 Output, c/i/o/&/_=Contacted metal (lowercase)

## Connectivity Matrix

| Silicon | VDD | VSS | Input2 | Internal1 | Output1 |
| --- | --- | --- | --- | --- | --- |
| NMOS1 |   | X |   |   |   |
| NMOS2 |   | X |   |   | X |
| NMOS3 |   | X |   | X |   |
| PMOS1 | X |   |   |   | X |
| PMOS2 |   |   |   | X |   |
| PMOS3 | X |   |   |   |   |
| Poly1 |   |   |   |   |   |
| Poly2 |   |   | X | X |   |
| Poly3 |   |   |   |   |   |
| Poly4 |   |   |   |   |   |

## Silicon Neighbourhood

| Silicon | Poly1 | Poly2 | Poly3 | Poly4 |
| --- | --- | --- | --- | --- |
| NMOS1 |   |   |   |   |
| NMOS2 | O |   |   |   |
| NMOS3 |   | O |   |   |
| PMOS1 | O |   |   |   |
| PMOS2 |   |   |   |   |
| PMOS3 |   |   |   |   |